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 MAC8SD, MAC8SM, MAC8SN
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors
Designed for industrial and consumer applications for full wave control of ac loads such as appliance controls, heater controls, motor controls, and other power switching applications.
Features
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* Sensitive Gate Allows Triggering by Microcontrollers and other * * * * * * * * *
Logic Circuits Uniform Gate Trigger Currents in Three Quadrants; Q1, Q2, and Q3 High Immunity to dv/dt - 25 V/ms Minimum at 110C High Commutating di/dt - 8.0 A/ms Minimum at 110C Maximum Values of IGT, VGT and IH Specified for Ease of Design On-State Current Rating of 8 Amperes RMS at 70C High Surge Current Capability - 70 Amperes Blocking Voltage to 800 Volts Rugged, Economical TO-220AB Package Pb-Free Packages are Available*
1 Unit V 400 600 800 IT(RMS) ITSM 8.0 70 A A 1 I2t PGM PG(AV) TJ Tstg 20 16 0.35 -40 to +110 -40 to +150 A2sec W W C C 2 3 4
TRIACS 8 AMPERES RMS 400 thru 800 VOLTS
MT2 G MT1
MARKING DIAGRAM
MAC8SxG AYWW 2 TO-220AB CASE 221A-09 STYLE 4 x A Y WW G = D, M, or N = Assembly Location = Year = Work Week = Pb-Free Package
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Peak Repetitive Off-State Voltage (Note 1) (TJ = -40 to 110C, Sine Wave, 50 to 60 Hz, Gate Open) MAC8SD MAC8SM MAC8SN On-State RMS Current (Full Cycle Sine Wave, 60 Hz, TC = 70C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 60 Hz, TJ = 110C) Circuit Fusing Consideration (t = 8.3 ms) Symbol VDRM, VRRM Value
3
PIN ASSIGNMENT
Main Terminal 1 Main Terminal 2 Gate Main Terminal 2
Peak Gate Power (Pulse Width 1.0 ms, TC = 70C) Average Gate Power (t = 8.3 ms, TC = 70C) Operating Junction Temperature Range Storage Temperature Range
ORDERING INFORMATION
Device MAC8SD MAC8SDG MAC8SM MAC8SMG MAC8SN MAC8SNG Package TO-220AB TO-220AB (Pb-Free) TO-220AB TO-220AB (Pb-Free) TO-220AB TO-220AB (Pb-Free) Shipping 50 Units / Rail 50 Units / Rail 50 Units / Rail 50 Units / Rail 50 Units / Rail 50 Units / Rail
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
Preferred devices are recommended choices for future use and best overall value.
1
December, 2005 - Rev. 5
Publication Order Number: MAC8S/D
MAC8SD, MAC8SM, MAC8SN
THERMAL CHARACTERISTICS
Characteristic Thermal Resistance, Junction-to-Case Junction-to-Ambient Symbol RqJC RqJA TL Value 2.2 62.5 260 Unit C/W C
Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted; Electricals apply in both directions)
Characteristic OFF CHARACTERISTICS Peak Repetitive Blocking Current (VD = Rated VDRM, VRRM; Gate Open) ON CHARACTERISTICS Peak On-State Voltage (Note ) (ITM = 11A) Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 W) MT2(+), G(+) MT2(+), G(-) MT2(-), G(-) Holding Current (VD = 12V, Gate Open, Initiating Current = 150mA) Latching Current (VD = 24V, IG = 5mA) MT2(+), G(+) MT2(-), G(-) MT2(+), G(-) Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100W) MT2(+), G(+) MT2(+), G(-) MT2(-), G(-) DYNAMIC CHARACTERISTICS Rate of Change of Commutating Current VD = 400 V, ITM = 3.5 A, Commutating dv/dt = 10 V m/sec, Gate Open, TJ = 110C, f = 500 Hz, Snubber: CS = 0.01 mF, RS =15 W, See Figure 16.) Critical Rate of Rise of Off-State Voltage (VD = Rate VDRM, Exponential Waveform, RGK = 510 W, TJ = 110C) 2. Indicates Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%. di/dt(c) 8.0 10 - A/ms VTM IGT - - - IH IL - - - VGT 0.45 0.45 0.45 0.62 0.60 0.65 1.5 1.5 1.5 5.0 10 5.0 15 20 15 V - 2.0 3.0 3.0 3.0 5.0 5.0 5.0 10 mA mA - - 1.85 V mA TJ = 25C TJ = 110C IDRM, IRRM mA - - - - 0.01 2.0 Symbol Min Typ Max Unit
dv/dt
25
75
-
V/ms
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2
MAC8SD, MAC8SM, MAC8SN
Voltage Current Characteristic of Triacs (Bidirectional Device)
+ Current Quadrant 1 MainTerminal 2 +
Symbol
VDRM IDRM VRRM IRRM VTM IH
Parameter
Peak Repetitive Forward Off State Voltage Peak Forward Blocking Current Peak Repetitive Reverse Off State Voltage Peak Reverse Blocking Current Maximum On State Voltage Holding Current Quadrant 3 MainTerminal 2 - IH VTM IRRM at VRRM on state IH
VTM
off state
+ Voltage IDRM at VDRM
Quadrant Definitions for a Triac
MT2 POSITIVE (Positive Half Cycle) +
(+) MT2
(+) MT2
Quadrant II
(-) IGT GATE MT1 REF
(+) IGT GATE MT1 REF
Quadrant I
IGT - (-) MT2 (-) MT2
+ IGT
Quadrant III
(-) IGT GATE MT1 REF
(+) IGT GATE MT1 REF
Quadrant IV
- MT2 NEGATIVE (Negative Half Cycle) All polarities are referenced to MT1. With in-phase signals (using standard AC lines) quadrants I and III are used.
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3
MAC8SD, MAC8SM, MAC8SN
P(AV), AVERAGE POWER DISSIPATION (WATTS) T C , MAXIMUM ALLOWABLE CASE TEMPERATURE (C) 110 25
a a
100 a = 30 and 60 90
a a
20
180 120
DC
a = CONDUCTION ANGLE 15 60
90
80
10 a = 30 5
a = CONDUCTION ANGLE 70
90 180 DC
60
0
2 4 6 8 10 IT(RMS), RMS ON-STATE CURRENT (AMPS)
12
0
0
2
4 6 8 10 IT(RMS), RMS ON-STATE CURRENT (AMPS)
12
Figure 1. RMS Current Derating
Figure 2. Maximum On-State Power Dissipation
R(t) , TRANSIENT THERMAL RESISTANCE (NORMALIZED)
I T, INSTANTANOUS ON-STATE CURRENT (AMPS)
100 Typical @ TJ = 25C Maximum @ TJ = 110C 10
1
ZqJC(t) = RqJC(t) r(t) 0.1
1 Maximum @ TJ = 25C
0.1
0.5
1
1.5 2 2.5 3 3.5 4 4.5 5 5.5 VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)
6
0.01 0.1
1
10 100 t, TIME (ms)
1000
1@ 4 10
Figure 3. On-State Characteristics
Figure 4. Transient Thermal Response
10 I H , HOLDING CURRENT (mA) I L , LATCHING CURRENT (mA)
25
8
20
6 MT2 NEGATIVE 4 MT2 POSITIVE 2
15
10
Q3
5 Q1
0
-40 -25
-10
5 20 35 50 65 80 TJ, JUNCTION TEMPERATURE (C)
95
110
0
-40 -25
-10
5 20 35 50 65 TJ, JUNCTION TEMPERATURE (C)
80
95
110
Figure 5. Typical Holding Current Versus Junction Temperature
Figure 6. Typical Latching Current Versus Junction Temperature
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4
MAC8SD, MAC8SM, MAC8SN
14 V GT, GATE TRIGGER VOLTAGE (VOLTS) IGT, GATE TRIGGER CURRENT (mA) 12 10 8 6 4 2 Q1 0 -40 -25 -10 5 20 35 50 65 TJ, JUNCTION TEMPERATURE (C) 80 95 110 Q2 Q3 1 0.9 Q3 0.8 0.7 0.6 0.5 Q2 0.4 0.3 -40 -25 -10 5 20 35 50 65 TJ, JUNCTION TEMPERATURE (C) 80 Q1 95 110 Q3 Q1
Figure 7. Typical Gate Trigger Current Versus Junction Temperature
Figure 8. Typical Gate Trigger Voltage Versus Junction Temperature
200 180 STATIC dv/dt (V/mS) 160 140 800 V 120 100 VPK = 400 V TJ = 110C
130 RG - MT1 = 510 W 120 STATIC dv/dt (V/mS) TJ = 100C
110 110C
600 V
100
90 80 60 100 80 200 300 400 500 600 700 800 RGK, GATE-MT1 RESISTANCE (OHMS) 900 1000 400 450 500 550 600 650 VPK, Peak Voltage (Volts)
120C
700
750
800
Figure 9. Typical Exponential Static dv/dt Versus Gate-MT1 Resistance, MT2(+)
Figure 10. Typical Exponential Static dv/dt Versus Peak Voltage, MT2(+)
130 120 VPK = 400 V STATIC dv/dt (V/mS) STATIC dv/dt (V/mS) 110 100 90 RG - MT1 = 510 W 80 70 100 105 TJ, Junction Temperature (C) 110 600 V 800 V
350
300 TJ = 100C 250 110C 200
150
RG - MT1 = 510 W
100
400
450
500
550 600 650 VPK, Peak Voltage (Volts)
700
750
800
Figure 11. Typical Exponential Static dv/dt Versus Junction Temperature, MT2(+)
Figure 12. Typical Exponential Static dv/dt Versus Peak Voltage, MT2(-)
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5
MAC8SD, MAC8SM, MAC8SN
350 300 STATIC dv/dt (V/mS) 250 200 150 RG - MT1 = 510 W 100 50 100 105 TJ, Junction Temperature (C) 110 100 VPK = 400 V 250 600 V 800 V STATIC dv/dt (V/mS) 600 V 200 800 V 150 TJ = 110C 100 200 300 400 500 600 700 800 RGK, GATE-MT1 RESISTANCE (OHMS) 900 1000 300 VPK = 400 V
Figure 13. Typical Exponential Static dv/dt Versus Junction Temperature, MT2(-)
(dv/dt)c , CRITICAL RATE OF RISE OF COMMUTATING VOLTAGE (V/ s) m
Figure 14. Typical Exponential Static dv/dt Versus Gate-MT1 Resistance, MT2(-)
100 VPK = 400 V
90C 10 100C
f= tw (di/dt)c = VDRM 6f ITM 1000 1 2 tw
110C
1 5 10 15 20 25 30 (di/dt)c, CRITICAL RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
1
Figure 15. Critical Rate of Rise of Commutating Voltage
LL 200 VRMS ADJUST FOR ITM, 60 Hz VAC TRIGGER CHARGE CONTROL TRIGGER CONTROL MEASURE I RS
1N4007
- CS MT2 1N914 51 W G MT1 ADJUST FOR + di/dt(c)
CHARGE
200 V
NON-POLAR CL
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 16. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
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6
MAC8SD, MAC8SM, MAC8SN
PACKAGE DIMENSIONS
TO-220AB CASE 221A-09 ISSUE AA
-T- B
4
SEATING PLANE
F T S
C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04
Q
123
A U K
H Z L V G D N R J
STYLE 4: PIN 1. 2. 3. 4.
MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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7
MAC8S/D


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